`include "top.vh"

module id_stage(
    input           clk           ,
    input           reset         ,
    //allowin
    input         es_allowin    ,
    output        ds_allowin    ,
    //from fs
    input         fs_to_ds_valid,
    input  [`fs_2_ds_bus_wid - 1:0] fs_to_ds_bus  ,
    //from ms
    input  [38:0] es_to_id_bus ,
    //from es
    input  [38:0] ms_to_id_bus ,
    //to es
    output         ds_to_es_valid,
    output [`ds_2_es_bus_wid - 1:0] ds_to_es_bus  ,
    //to fs
    output [33:0] br_bus        ,
    //from wb to rf: for write back
    input  [38:0] ws_to_id_bus,
    //csr data conflict
    input  [ 2:0] es_ms_ws_read_csr,
    //interrupt
    input  has_int,
    //ws_ex
    input  ws_ex,
    input  ws_ertn_flush
);

reg         ds_valid   ;
wire        ds_ready_go;

reg  [`fs_2_ds_bus_wid - 1:0] fs_to_ds_bus_reg;

wire [31:0] ds_inst;
wire [31:0] ds_pc  ;
wire fs_ex;
wire [`EX_SIG_wid-1:0]fs_ex_signal;
assign {ds_inst,
        ds_pc,
        fs_ex,
        fs_ex_signal  } = fs_to_ds_bus_reg;

wire        br_taken;
wire [31:0] br_target;
wire        rj_eq_rd;
wire        rj_ls_rd_sig;       //signed rf less than rd
wire        rj_ls_rd_usig;      //unsigned rf less than rd
wire [31:0] br_offs;
wire [31:0] jirl_offs;
wire        br_stall;

wire [11:0] alu_op;
wire        src1_is_pc;
wire        src2_is_imm;
wire        res_from_mem;
wire        dst_is_r1;
wire        dst_is_rj;
wire        gr_we;
wire        mem_we;
wire        src_reg_is_rd;
wire [4: 0] dest;
wire [31:0] rj_value;
wire [31:0] rkd_value;
wire [31:0] imm;

wire [ 3:0] mem_op;         //{inst_ld, ld_sig, ld or st op[1:0]}

wire [ 5:0] op_31_26;
wire [ 3:0] op_25_22;
wire [ 1:0] op_21_20;
wire [ 4:0] op_19_15;
wire [ 4:0] rd;
wire [ 4:0] rj;
wire [ 4:0] rk;
wire [11:0] i12;
wire [19:0] i20;
wire [15:0] i16;
wire [25:0] i26;

wire [63:0] op_31_26_d;
wire [15:0] op_25_22_d;
wire [ 3:0] op_21_20_d;
wire [31:0] op_19_15_d;

wire        inst_add_w;
wire        inst_sub_w;
wire        inst_slt;
wire        inst_sltu;
wire        inst_nor;
wire        inst_and;
wire        inst_or;
wire        inst_xor;
wire        inst_slli_w;
wire        inst_srli_w;
wire        inst_srai_w;
wire        inst_addi_w;
wire        inst_ld_w;
wire        inst_st_w;
wire        inst_jirl;
wire        inst_b;
wire        inst_bl;
wire        inst_beq;
wire        inst_bne;
wire        inst_lu12i_w;
wire        inst_slti;
wire        inst_sltui;
wire        inst_andi;
wire        inst_ori;
wire        inst_xori;
wire        inst_sll;
wire        inst_srl;
wire        inst_sra;
wire        inst_pcaddu12i;
wire        inst_mul_w;
wire        inst_mulh_w;
wire        inst_mulh_wu;
wire        inst_div_w;
wire        inst_mod_w;
wire        inst_div_wu;
wire        inst_mod_wu;
wire        inst_blt;
wire        inst_bge;
wire        inst_bltu;
wire        inst_bgeu;
wire        inst_ld_b;
wire        inst_ld_h;
wire        inst_ld_bu;
wire        inst_ld_hu;
wire        inst_st_b;
wire        inst_st_h;
wire        inst_csrrd;
wire        inst_csrwr;
wire        inst_csrxchg;
wire        inst_syscall;
wire        inst_ertn;
wire        inst_break;
wire        inst_rdcntid;
wire        inst_rdcntvl_w;
wire        inst_rdcntvh_w;

wire        inst_ld_type;
wire        inst_st_type;
wire        inst_br_type;



wire        need_ui5;
wire        need_si12;
wire        need_si16;
wire        need_si20;
wire        need_si26;
wire        src2_is_4;
wire        need_si12_zero;

wire [ 4:0] rf_raddr1;
wire [31:0] rf_rdata1;
wire [ 4:0] rf_raddr2;
wire [31:0] rf_rdata2;
wire        rf_we   ;
wire [ 4:0] rf_waddr;
wire [31:0] rf_wdata;

wire [31:0] alu_src1   ;
wire [31:0] alu_src2   ;
wire [31:0] alu_result ;

wire read_rd;
wire read_rj;
wire read_rk;

wire [2:0] read_after_write_addr1;
wire [2:0] read_after_write_addr2;

wire [4:0] ws_dest;

wire [31:0] es_alu_result;
wire        es_gr_we;
wire [ 4:0] es_dest;
wire        es_res_from_mem;

wire [31:0] ms_final_result;
wire        ms_gr_we;
wire [ 4:0] ms_dest;
wire ws_rf_we;

wire [13:0] csr_num;
wire [31:0] csr_wvalue;
wire [31:0] csr_wmask;
wire csr_re, csr_we, csr_need_mask;
wire [`CSR_SIG_wid-1:0] csr_signal;
wire es_read_csr, ms_read_csr, ws_read_csr;
wire csr_data_block;
wire ds_ex, ds_ertn;
wire [`EX_SIG_wid-1:0] ds_ex_signal;
wire ex_sys, ex_brk, ex_int, ex_ine;

assign ds_ex = fs_ex || ex_sys || ex_brk || has_int || ex_ine;
assign ex_sys = inst_syscall;
assign ex_brk = inst_break;
assign ex_int = has_int;
assign ex_ine = ~inst_add_w & ~inst_sub_w & ~inst_slt & ~inst_sltu & ~inst_nor & ~inst_and & ~inst_or & ~inst_xor & ~inst_slli_w & ~inst_srli_w & ~inst_srai_w & ~inst_addi_w & ~inst_ld_w & ~inst_st_w & ~inst_jirl & ~inst_b & ~inst_bl & ~inst_beq & ~inst_bne & ~inst_lu12i_w & ~inst_slti & ~inst_sltui & ~inst_andi & ~inst_ori & ~inst_xori & ~inst_sll & ~inst_srl & ~inst_sra & ~inst_pcaddu12i & ~inst_mul_w & ~inst_mulh_w & ~inst_mulh_wu & ~inst_div_w & ~inst_mod_w & ~inst_div_wu & ~inst_mod_wu & ~inst_blt & ~inst_bge & ~inst_bltu & ~inst_bgeu & ~inst_ld_b & ~inst_ld_h & ~inst_ld_bu & ~inst_ld_hu & ~inst_st_b & ~inst_st_h & ~inst_csrrd & ~inst_csrwr & ~inst_csrxchg & ~inst_syscall & ~inst_ertn & ~inst_break & ~inst_rdcntid & ~inst_rdcntvl_w & ~inst_rdcntvh_w;
assign ds_ex_signal =   fs_ex  ? fs_ex_signal :
                        ex_sys ? `EX_SIG_SYS :
                        ex_brk ? `EX_SIG_BRK :
                        ex_int ? `EX_SIG_INT :
                        ex_ine ? `EX_SIG_INE :
                        4'h0;

assign csr_re = inst_csrrd || inst_csrwr || inst_csrxchg || inst_rdcntid;
assign csr_we = inst_csrwr || inst_csrxchg;
assign csr_need_mask = inst_csrxchg;
assign csr_num    = inst_rdcntid ? `CSR_TID : ds_inst[23:10];
assign csr_wvalue = rkd_value;
assign csr_wmask  = rj_value;
assign csr_signal = {csr_re, csr_we, csr_need_mask, csr_num, csr_wvalue, csr_wmask};
assign ds_ertn = inst_ertn;

assign {es_read_csr, ms_read_csr, ws_read_csr} = es_ms_ws_read_csr;

assign br_bus       = {br_stall,br_taken,br_target};

assign ds_to_es_bus = {
                       inst_rdcntvl_w,
                       inst_rdcntvh_w,
                       csr_signal,  //81
                       ds_ex,          //1
                       ds_ex_signal,//16
                       ds_ertn,        //1

                       alu_op,      //12
                       mem_op,      //3
                       gr_we,       //1
                       dest,        //5
					   rkd_value,   //32
                       ds_pc,       //32
                       alu_src1,    //32
                       alu_src2,    //32
                       inst_mul_w,  //1
                       inst_mulh_w, //1
                       inst_mulh_wu,//1
                       inst_div_w,  //1
                       inst_div_wu, //1
                       inst_mod_w,  //1
                       inst_mod_wu  //1
                      };

always @(posedge clk ) begin//ID reg
    if (ds_allowin) begin
        fs_to_ds_bus_reg <= fs_to_ds_bus; 
    end
end

assign read_rk = inst_add_w | inst_sub_w | inst_slt | inst_sltu | inst_and | inst_or | inst_nor | inst_xor 
                | inst_sll | inst_srl | inst_sra 
                | inst_mul_w | inst_mulh_w | inst_mulh_wu | inst_div_w | inst_div_wu | inst_mod_w | inst_mod_wu;

assign read_rj = ~inst_lu12i_w & ~inst_b & ~inst_bl & ~inst_pcaddu12i;
assign read_rd = inst_br_type | inst_st_type | inst_csrwr | inst_csrxchg;

assign ds_ready_go = (!( (read_after_write_addr1[2]) && es_res_from_mem) && !csr_data_block || ws_ex) & !ms_block;
assign ds_allowin = (~ds_valid) | (ds_ready_go & es_allowin);
assign ds_to_es_valid = ds_valid & ds_ready_go;

assign read_after_write_addr1 = {3{read_rj&&(rf_raddr1!=5'b0)}}&{ (es_rf_we)&&(es_dest ==rf_raddr1),
                                                                       (ms_rf_we)&&(ms_dest ==rf_raddr1),
                                                                       (ws_rf_we   )&&(ws_dest==rf_raddr1)};
assign read_after_write_addr2 = {3{(read_rd || read_rk)&&rf_raddr2!=5'b0}}&{ (es_rf_we)&&(es_dest ==rf_raddr2),
                                                                       (ms_rf_we)&&(ms_dest ==rf_raddr2),
                                                                       (ws_rf_we   )&&(ws_dest==rf_raddr2)};

assign csr_data_block = (es_read_csr & (read_after_write_addr1[2] | read_after_write_addr2[2])) ||
                        (ms_read_csr & (read_after_write_addr1[1] | read_after_write_addr2[1])) ||
                        (ws_read_csr & (read_after_write_addr1[0] | read_after_write_addr2[0]));

always @(posedge clk ) begin
    if (reset) begin
        ds_valid <= 1'b0;
    end
    else if (ws_ex || ws_ertn_flush)
        ds_valid <= 1'b0;
    else if(br_taken)begin
        ds_valid <= 1'b0;
    end
    else if (ds_allowin) begin
        ds_valid <= fs_to_ds_valid;
    end
end

assign {es_res_from_mem,es_alu_result,es_rf_we,es_dest} = es_to_id_bus;

assign {ms_block,ms_final_result,ms_rf_we,ms_dest} = ms_to_id_bus;


assign {
        ws_rf_we,   //38
        rf_we   ,  //37
        rf_waddr,  //36:32
        rf_wdata   //31:0
    } = ws_to_id_bus;
 assign ws_dest = rf_waddr;

assign op_31_26  = ds_inst[31:26];
assign op_25_22  = ds_inst[25:22];
assign op_21_20  = ds_inst[21:20];
assign op_19_15  = ds_inst[19:15];

assign rd   = ds_inst[ 4: 0];
assign rj   = ds_inst[ 9: 5];
assign rk   = ds_inst[14:10];

assign i12  = ds_inst[21:10];
assign i20  = ds_inst[24: 5];
assign i16  = ds_inst[25:10];
assign i26  = {ds_inst[ 9: 0], ds_inst[25:10]};

decoder_6_64 u_dec0(.in(op_31_26 ), .out(op_31_26_d ));
decoder_4_16 u_dec1(.in(op_25_22 ), .out(op_25_22_d ));
decoder_2_4  u_dec2(.in(op_21_20 ), .out(op_21_20_d ));
decoder_5_32 u_dec3(.in(op_19_15 ), .out(op_19_15_d ));

assign inst_add_w  = op_31_26_d[6'h00] & op_25_22_d[4'h0] & op_21_20_d[2'h1] & op_19_15_d[5'h00];
assign inst_sub_w  = op_31_26_d[6'h00] & op_25_22_d[4'h0] & op_21_20_d[2'h1] & op_19_15_d[5'h02];
assign inst_slt    = op_31_26_d[6'h00] & op_25_22_d[4'h0] & op_21_20_d[2'h1] & op_19_15_d[5'h04];
assign inst_sltu   = op_31_26_d[6'h00] & op_25_22_d[4'h0] & op_21_20_d[2'h1] & op_19_15_d[5'h05];
assign inst_nor    = op_31_26_d[6'h00] & op_25_22_d[4'h0] & op_21_20_d[2'h1] & op_19_15_d[5'h08];
assign inst_and    = op_31_26_d[6'h00] & op_25_22_d[4'h0] & op_21_20_d[2'h1] & op_19_15_d[5'h09];
assign inst_or     = op_31_26_d[6'h00] & op_25_22_d[4'h0] & op_21_20_d[2'h1] & op_19_15_d[5'h0a];
assign inst_xor    = op_31_26_d[6'h00] & op_25_22_d[4'h0] & op_21_20_d[2'h1] & op_19_15_d[5'h0b];
assign inst_slli_w = op_31_26_d[6'h00] & op_25_22_d[4'h1] & op_21_20_d[2'h0] & op_19_15_d[5'h01];
assign inst_srli_w = op_31_26_d[6'h00] & op_25_22_d[4'h1] & op_21_20_d[2'h0] & op_19_15_d[5'h09];
assign inst_srai_w = op_31_26_d[6'h00] & op_25_22_d[4'h1] & op_21_20_d[2'h0] & op_19_15_d[5'h11];
assign inst_addi_w = op_31_26_d[6'h00] & op_25_22_d[4'ha];
assign inst_ld_w   = op_31_26_d[6'h0a] & op_25_22_d[4'h2];
assign inst_st_w   = op_31_26_d[6'h0a] & op_25_22_d[4'h6];
assign inst_jirl   = op_31_26_d[6'h13];
assign inst_b      = op_31_26_d[6'h14];
assign inst_bl     = op_31_26_d[6'h15];
assign inst_beq    = op_31_26_d[6'h16];
assign inst_bne    = op_31_26_d[6'h17];
assign inst_lu12i_w= op_31_26_d[6'h05] & ~ds_inst[25];
assign inst_slti   = op_31_26_d[6'h00] & op_25_22_d[4'h8];
assign inst_sltui  = op_31_26_d[6'h00] & op_25_22_d[4'h9];
assign inst_andi   = op_31_26_d[6'h00] & op_25_22_d[4'hd];
assign inst_ori    = op_31_26_d[6'h00] & op_25_22_d[4'he];
assign inst_xori   = op_31_26_d[6'h00] & op_25_22_d[4'hf];
assign inst_sll    = op_31_26_d[6'h00] & op_25_22_d[4'h0] & op_21_20_d[2'h1] & op_19_15_d[5'h0e];
assign inst_srl    = op_31_26_d[6'h00] & op_25_22_d[4'h0] & op_21_20_d[2'h1] & op_19_15_d[5'h0f];
assign inst_sra    = op_31_26_d[6'h00] & op_25_22_d[4'h0] & op_21_20_d[2'h1] & op_19_15_d[5'h10];
assign inst_pcaddu12i= op_31_26_d[6'h07];
assign inst_mul_w  = op_31_26_d[6'h00] & op_25_22_d[4'h0] & op_21_20_d[2'h1] & op_19_15_d[5'h18];
assign inst_mulh_w = op_31_26_d[6'h00] & op_25_22_d[4'h0] & op_21_20_d[2'h1] & op_19_15_d[5'h19];
assign inst_mulh_wu= op_31_26_d[6'h00] & op_25_22_d[4'h0] & op_21_20_d[2'h1] & op_19_15_d[5'h1a];
assign inst_div_w  = op_31_26_d[6'h00] & op_25_22_d[4'h0] & op_21_20_d[2'h2] & op_19_15_d[5'h00];
assign inst_div_wu = op_31_26_d[6'h00] & op_25_22_d[4'h0] & op_21_20_d[2'h2] & op_19_15_d[5'h02];
assign inst_mod_w  = op_31_26_d[6'h00] & op_25_22_d[4'h0] & op_21_20_d[2'h2] & op_19_15_d[5'h01];
assign inst_mod_wu = op_31_26_d[6'h00] & op_25_22_d[4'h0] & op_21_20_d[2'h2] & op_19_15_d[5'h03];
assign inst_blt    = op_31_26_d[6'h18];
assign inst_bge    = op_31_26_d[6'h19];
assign inst_bltu   = op_31_26_d[6'h1a];
assign inst_bgeu   = op_31_26_d[6'h1b];
assign inst_ld_b   = op_31_26_d[6'h0a] & op_25_22_d[4'h0];
assign inst_ld_h   = op_31_26_d[6'h0a] & op_25_22_d[4'h1];
assign inst_ld_bu  = op_31_26_d[6'h0a] & op_25_22_d[4'h8];
assign inst_ld_hu  = op_31_26_d[6'h0a] & op_25_22_d[4'h9];
assign inst_st_b   = op_31_26_d[6'h0a] & op_25_22_d[4'h4];
assign inst_st_h   = op_31_26_d[6'h0a] & op_25_22_d[4'h5];
assign inst_csrrd   = op_31_26_d[6'h01] & !ds_inst[25:24] & rj == 5'b0;
assign inst_csrwr   = op_31_26_d[6'h01] & !ds_inst[25:24] & rj == 5'b1;
assign inst_csrxchg = op_31_26_d[6'h01] & !ds_inst[25:24] & rj != 5'b0 & rj != 5'b1;
assign inst_syscall = op_31_26_d[6'h00] & op_25_22_d[4'h0] & op_21_20_d[2'h2] & op_19_15_d[5'h16];
assign inst_break   = op_31_26_d[6'h00] & op_25_22_d[4'h0] & op_21_20_d[2'h2] & op_19_15_d[5'h14];
assign inst_ertn    = op_31_26_d[6'h01] & op_25_22_d[4'h9] & op_21_20_d[2'h0] & op_19_15_d[5'h10] & (ds_inst[14:10] == 5'b01110) & ~ds_inst[9:0];
assign inst_rdcntid = op_31_26_d[6'h0] & op_25_22_d[4'h0] & op_21_20_d[2'h0] & op_19_15_d[5'h0] & (rk == 5'b11000) & (rd == 5'b0);
assign inst_rdcntvl_w = op_31_26_d[6'h0] & op_25_22_d[4'h0] & op_21_20_d[2'h0] & op_19_15_d[5'h0] & (rk == 5'b11000) & (rj == 5'b0);
assign inst_rdcntvh_w = op_31_26_d[6'h0] & op_25_22_d[4'h0] & op_21_20_d[2'h0] & op_19_15_d[5'h0] & (rk == 5'b11001) & (rj == 5'b0);

assign inst_ld_type = inst_ld_b | inst_ld_bu| inst_ld_h | inst_ld_hu| inst_ld_w;
assign inst_st_type = inst_st_b | inst_st_h | inst_st_w;
assign inst_br_type = inst_beq  | inst_bne  | inst_blt  | inst_bltu | inst_bge  | inst_bgeu;


assign alu_op[ 0] = inst_add_w | inst_addi_w | inst_ld_type | inst_st_type
                    | inst_jirl | inst_bl
                    | inst_pcaddu12i;
assign alu_op[ 1] = inst_sub_w;
assign alu_op[ 2] = inst_slt|inst_slti;
assign alu_op[ 3] = inst_sltu|inst_sltui;
assign alu_op[ 4] = inst_and|inst_andi;
assign alu_op[ 5] = inst_nor;
assign alu_op[ 6] = inst_or|inst_ori;
assign alu_op[ 7] = inst_xor|inst_xori;
assign alu_op[ 8] = inst_slli_w|inst_sll;
assign alu_op[ 9] = inst_srli_w|inst_srl;
assign alu_op[10] = inst_srai_w|inst_sra;
assign alu_op[11] = inst_lu12i_w;

assign mem_op[ 3] = res_from_mem;       // = inst_ld_type
assign mem_op[ 2] = inst_ld_w | inst_ld_h | inst_ld_b;  //1 for sig, 0 for unsig
assign mem_op[ 1] = inst_ld_w | inst_st_w | inst_ld_h | inst_ld_hu | inst_st_h;
assign mem_op[ 0] = inst_ld_w | inst_st_w | inst_ld_b | inst_ld_bu | inst_st_b;

assign need_ui5   =  inst_slli_w | inst_srli_w | inst_srai_w;
assign need_si12  =  inst_addi_w | inst_ld_w | inst_st_w | inst_slti | inst_sltui;
assign need_si16  =  inst_jirl | inst_beq | inst_bne;
assign need_si20  =  inst_lu12i_w | inst_pcaddu12i;
assign need_si26  =  inst_b | inst_bl;
assign src2_is_4  =  inst_jirl | inst_bl;
assign need_si12_zero = inst_ori | inst_xori | inst_andi;

assign imm = src2_is_4 ? 32'h4                      :
             need_si20 ? {i20,12'b0}                :
             need_si12_zero ? {20'b0,i12}           :
/*need_ui5 || need_si12*/{{20{i12[11]}}, i12[11:0]} ;

assign br_offs = need_si26 ? {{ 4{i26[25]}}, i26[25:0], 2'b0} :
                             {{14{i16[15]}}, i16[15:0], 2'b0} ;

assign jirl_offs = {{14{i16[15]}}, i16[15:0], 2'b0};

assign src_reg_is_rd = read_rd;

assign src1_is_pc    = inst_jirl | inst_bl | inst_pcaddu12i;

assign src2_is_imm   = inst_slli_w |
                       inst_srli_w |
                       inst_srai_w |
                       inst_addi_w |
                       inst_ld_type|
                       inst_st_type|
                       inst_lu12i_w|
                       inst_jirl   |
                       inst_bl     |
                       inst_slti   |
                       inst_sltui  |
                       inst_andi   |
                       inst_ori    |
                       inst_xori   |
                       inst_pcaddu12i;

assign res_from_mem  = inst_ld_type;
assign dst_is_r1     = inst_bl;
assign dst_is_rj     = inst_rdcntid;
assign gr_we         = ~inst_st_type & ~inst_br_type & ~inst_b;
assign mem_we        = inst_st_w;
assign dest          = dst_is_r1 ? 5'd1 : 
                       dst_is_rj ? rj : 
                       rd;

assign rf_raddr1 = rj;
assign rf_raddr2 = src_reg_is_rd ? rd :rk;
regfile u_regfile(
    .clk    (clk      ),
    .raddr1 (rf_raddr1),
    .rdata1 (rf_rdata1),
    .raddr2 (rf_raddr2),
    .rdata2 (rf_rdata2),
    .we     (rf_we    ),
    .waddr  (rf_waddr ),
    .wdata  (rf_wdata )
    );

assign rj_value  = read_after_write_addr1[2]? es_alu_result:
                   read_after_write_addr1[1]? ms_final_result:
                   read_after_write_addr1[0]? rf_wdata       :
                                              rf_rdata1      ; 
assign rkd_value = read_after_write_addr2[2]? es_alu_result:
                   read_after_write_addr2[1]? ms_final_result:
                   read_after_write_addr2[0]? rf_wdata       :
                                              rf_rdata2      ; 
assign rj_eq_rd     = (rj_value == rkd_value);
assign rj_ls_rd_usig= (rj_value <  rkd_value);
assign rj_ls_rd_sig =   rj_value[31] & ~rkd_value[31]                       //rj neg, rd pos
                    ||  ~(rj_value[31] ^ rkd_value[31]) & rj_ls_rd_usig;    //same sig, compare

assign br_taken =  (  inst_beq  &&  rj_eq_rd
                   || inst_bne  && !rj_eq_rd
                   || inst_blt  &&  rj_ls_rd_sig
                   || inst_bge  && !rj_ls_rd_sig
                   || inst_bltu &&  rj_ls_rd_usig
                   || inst_bgeu && !rj_ls_rd_usig
                   || inst_jirl
                   || inst_bl
                   || inst_b) && ds_valid && ds_ready_go;
                   
assign br_target = (inst_br_type || inst_bl || inst_b) ? (ds_pc + br_offs) :
                                                   /*inst_jirl*/ (rj_value + jirl_offs);
assign br_stall  = inst_br_type & ((read_after_write_addr1[2] | read_after_write_addr1 [1] | read_after_write_addr1 [0] ) | (read_after_write_addr2[2] | read_after_write_addr2 [1] | read_after_write_addr2 [0] ));
assign alu_src1 = src1_is_pc  ? ds_pc[31:0] : rj_value;
assign alu_src2 = src2_is_imm ? imm : rkd_value;
endmodule